This invention relates to a semiconductor device comprising a high resistance layer made of polycrystal silicon.
An E/R (enhancement/resistor) type static memory cell is known as a semiconductor static memory cell. The E/R type static memory cell comprises a high resistance element made of polycrystal silicon.
As shown in FIG. 1, the E/R type static memory cell comprises a flip-flop, an access gate and a pair of load resistors of a high resistance. The flip-flop comprises MOS (metal oxide semiconductor) transistors 1 and 2 of an enhancement type. The access gate comprises MOS transistors 3 and 4 of an enhancement type. The load resistors comprise resistors 5 and 6. Vcc and Vss denote high and low power source potentials, respectively. B and Bindicate bit lines. W denotes a word line. In FIG. 2, reference numeral 10 denotes a word line layer. First polycrystal silicon layer 11 is highly doped with an impurity and has a low resistance. Second polycrystal silicon layer 12 comprises high resistance region 12A, and low resistance region 12B, highly doped with an impurity. Silicon layer 11 and high resistance region 12A contact each other within contact hole 13.sub.1. Bit line layers 14.sub.1 and 14.sub.2, made of aluminium, cross over contact holes 13.sub.1 and 13.sub.2, respectively. Low resistance region 12B is used as a Vcc line. Reference numeral 15 denotes N Conductivity type, impurity diffused semiconductor regions. In FIG. 3, reference numeral 21 denotes N conductivity type substrate. P conductivity type well layer 22, made of single crystal silicon, is formed on substrate 21. N.sup.+ conductivity type, impurity diffused regions 15 are formed in well layer 22. Reference numeral 23 denotes gate insulation film made of SiO.sub.2. Reference numeral 24 denotes field insulation film made of SiO.sub.2. Silicon layer 11 is formed on semiconductor region 15. Reference numeral 25 denotes field insulation film made of SiO.sub.2, having contact hole 13.sub.1 formed therein. Insulation film 26, made of SiO.sub.2, is formed on insulation film 25 and silicon layer 12. Bit line layer 14.sub.1 contacts N conductivity type, impurity diffused region 15, and extends onto insulation film 25. Passivation film 27 is formed on bit line layer 14.sub.1.
In manufacturing the device shown in FIGS. 2 and 3, insulation film 26, made of SiO.sub.2, bit line layer 14.sub.1 and passivation film 27 are formed after insulation film 25 is formed. Forming insulation film 26, bit line layer 14.sub.1 and passivation film 27 comprises a thermal treatment step. The thermal treatment diffuses impurities, doped in low resistance region 12B, into high resistance region 12A by the portion whose length is shown by L1. The thermal treatment also diffuses impurities, doped in low resistance layer 11, into high resistance region 12A by the portion whose length is shown by L2. Therefore, the effective region of high resistance region 12A is shortened by the portions whose lengths are shown by L1 and 12. The length of the effective region is shown by L0. The effective region of silicon layer 12 determines the power consumption in the memory cell. The shorter the effective region is, the larger the power consumption is. In order to reduce layer 12 longer. This, however, makes the memory cell size large and the packing density low.